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VNQ5050AK-E
Quad channel high side driver with analog current sense for automotive applications
Features
Max supply voltage Operating voltage range Max on-state resistance (per ch.) Current limitation (typ) Off state supply current
1. Typical value with all loads connected.
VCC
41V
VCC 4.5 to 36V RON ILIMH IS 50 m 19 A 2 A(1)
PowerSSO-24
Application

All types of resistive, inductive and capacitive loads. Suitable as LED driver.
General features: - Inrush current active management by power limitation - Very low stand-by current - 3.0V CMOS compatible input - Optimized electromagnetic emission - Very low electromagnetic susceptibility - In compliance with the 2002/95/EC European directive Diagnostic functions: - Proportional load current sense - High current sense precision for wide current range - Current sense disable - Thermal shutdown indication - Very low current sense leakage Protection: - Undervoltage shut-down - Overvoltage clamp - Load current limitation - Self limiting of fast thermal transients - Protection against loss of ground and loss of VCC - Thermal shut down - Reverse battery protection (see Figure 25) - Electrostatic discharge protection Table 1. Device summary
Description
The VNQ5050AK-E is a monolithic device made using STMicroelectronics VIPower M0-5 technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to a safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as the fault condition disappears.
Order codes Package Tube PowerSSO-24 VNQ5050AK-E Tape and Reel VNQ5050AKTR-E
December 2007
Rev 6
1/31
www.st.com 31
Contents
VNQ5050AK-E
Contents
1 2 Block diagram and pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 2.2 2.3 2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 20
3.1.1 3.1.2 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 20 Solution 2: a diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . 21
3.2 3.3 3.4
Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23
4
Package and PC board thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1 PowerSSO-24 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5
Package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 5.2 5.3 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PowerSSO-24TM mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2/31
VNQ5050AK-E
List of tables
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and n.c. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC=13V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Current sense (8V3/31
List of figures
VNQ5050AK-E
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IOUT/ISENSE Vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 On state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 On state resistance vs. VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ILIMH vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Maximum turn off current versus inductance (for each channel) . . . . . . . . . . . . . . . . . . . . 23 PowerSSO-24 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Rthj-amb vs. PCB copper area in open box free air condition (one channel ON). . . . . . . . 24 PowerSSO-24 thermal impedance junction ambient single pulse (one channel on) . . . . . 25 Thermal fitting model of a double channel HSD in PowerSSO-24 . . . . . . . . . . . . . . . . . . . 25 PowerSSO-24TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 PowerSSO-24 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PowerSSO-24 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4/31
VNQ5050AK-E
Block diagram and pin configuration
1
Block diagram and pin configuration
Figure 1. Block diagram
VCC
VCC CLAMP GND INPUT1 LOGIC INPUT2
UNDERVOLTAGE OUTPUT1 PwCLAMP 1 DRIVER 1 ILIM 1 VDSLIM 1 OVERTEMP. 1
INPUT2
VCC Control & Protection
CURRENT SENSE1
CURRENT Equivalent to SENSE2 channel1
OUTPUT2 VCC CURRENT SENSE2 OUTPUT3 VCC CURRENT SENSE3 OUTPUT4 CURRENT SENSE4
INPUT3 INPUT4
IOUT1 K1
INPUT3
CURRENT Equivalent to SENSE3 channel1 INPUT4
Control & Protection
PwrLIM 1 CS_DIS
CURRENT Equivalent to SENSE4 channel1
Control & Protection
Table 2.
Name VCC
Pin functions
Function Battery connection Power output Ground connection. Must be reverse battery protected by an external diode/resistor network Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state Analog current sense pin, delivers a current proportional to the load current Active high CMOS compatible pin, to disable the current sense pin
OUTPUTn GND INPUTn CURRENT SENSEn CS_DIS
5/31
Block diagram and pin configuration Figure 2. Configuration diagram (top view)
VNQ5050AK-E
VCC GND INPUT1 CURRENT SENSE1 INPUT2 CURRENT SENSE2 INPUT3 CURRENT SENSE3 INPUT4 CURRENT SENSE4 CS_DIS. VCC
OUTPUT1 OUTPUT1 OUTPUT1 OUTPUT2 OUTPUT2 OUTPUT2 OUTPUT3 OUTPUT3 OUTPUT3 OUTPUT4 OUTPUT4 OUTPUT4
TAB = VCC
Table 3.
Suggested connections for unused and n.c. pins
Current sense N.R.(1) Through 1k resistor N.C. X X Output X N.R. Input X Through 10k resistor CS_DIS X Through 10k resistor
Connection / pin Floating To ground
1. Not recommended.
6/31
VNQ5050AK-E
Electrical specifications
2
Electrical specifications
Figure 3. Current and voltage conventions
IS VCC ICSD VCSD CS_DIS VFn IOUTn OUTPUTn VOUTn VCC
IINn VINn INPUTn GND CURRENT SENSEn
ISENSEn VSENSEn
IGND
Note:
VFn = VOUTn - VCC during reverse battery condition.
2.1
Absolute maximum ratings
Stressing the device above the ratings listed in the "Absolute maximum ratings" tables may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in this section for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 4.
Symbol VCC -VCC - IGND IOUT - IOUT IIN ICSD DC supply voltage Reverse DC supply voltage DC reverse ground pin current DC output current Reverse DC output current DC input current DC current sense disable input current
Absolute maximum ratings
Parameter Value 41 0.3 200 Internally limited 20 -1 to 10 -1 to 10 200 VCC-41 +VCC 104 Unit V V mA A A mA mA mA V V mJ
-ICSENSE DC Reverse CS pin current VCSENSE Current sense maximum voltage EMAX Maximum switching energy (single pulse) (L=3 mH; RL=0; Vbat=13.5V; Tjstart=150C; IOUT = IlimL(Typ.) )
7/31
Electrical specifications Table 4.
Symbol
VNQ5050AK-E
Absolute maximum ratings (continued)
Parameter Electrostatic discharge (human body model: R=1.5K; C=100pF) - INPUT - CURRENT SENSE - CS_DIS - OUTPUT - VCC Charge device model (CDM-AEC-Q100-011) Junction operating temperature Storage temperature Value Unit
VESD
4000 2000 4000 5000 5000 750 -40 to 150 -55 to 150
V V V V V V C C
VESD Tj Tstg
2.2
Thermal data
Table 5.
Symbol Rthj-case Rthj-amb
Thermal data
Parameter Thermal resistance junction-case (With one channel ON) Thermal resistance junction-ambient Max value 2.8 See Figure 29. Unit C/W C/W
8/31
VNQ5050AK-E
Electrical specifications
2.3
Electrical characteristics
Values specified in this section are for 8VSymbol VCC VUSD VUSDhyst
Power section
Parameter Operating supply voltage Undervoltage shutdown Undervoltage shut-down hysteresis On state resistance Clamp voltage IOUT=2A; Tj=25C IOUT=2A; Tj=150C IOUT=2A; VCC=5V; Tj=25C IS=20 mA Off State; VCC=13V; Tj=25C; VIN=VOUT=VSENSE=VCSD=0V On State; VCC=13V; VIN=5V; IOUT=0A 0 0 41 46 Test conditions Min. Typ. 4.5 13 3.5 0.5 50 100 65 52 Max. 36 4.5 Unit V V V m m m V
RON Vclamp
IS
Supply current
2(1) 8
5(1) 14
A mA
IL(off)
VIN=VOUT=0V; VCC=13V; Tj=25C Off state output current(2) VIN=VOUT=0V; VCC=13V; Tj=125C Output - VCC diode voltage(2) -IOUT=2A; Tj=150C
0.01
3 5 0.7
A
VF
V
1. PowerMOS leakage included. 2. For each channel.
Table 7.
Symbol td(on) td(off)
Switching (VCC=13V)
Parameter Turn-on delay time Turn-off delay time Test conditions RL= 6.5 (see Figure 6.) RL= 6.5 (see Figure 6.) RL= 6.5 RL= 6.5 RL= 6.5 (see Figure 6.) RL= 6.5 (see Figure 6.) Min. Typ. 20 45 See Figure 19. See Figure 21. 0.15 0.3 Max. Unit s s V/ s V/ s mJ mJ
(dVOUT/dt)on Turn-on voltage slope (dVOUT/dt)off Turn-off voltage slope WON WOFF Switching energy losses during twon Switching energy losses during twoff
9/31
Electrical specifications Table 8.
Symbol
VNQ5050AK-E
Current sense (8VParameter Test conditions IOUT= 0.05A; VSENSE= 0.5 V; VCSD=0 V; Tj= -40C...150C IOUT= 1A; VSENSE= 0.5 V; VCSD=0 V; Tj= -40C...150C Tj= 25C...150C Min. Typ. Max. Unit
K0
IOUT/ISENSE
1340 2420 3460
K1
IOUT/ISENSE
1370 1860 2510 1510 1860 2210 -10 10 %
dK1/K1(1)
IOUT= 1A; VSENSE= 0.5V; Current sense ratio drift VCSD= 0V; TJ= -40 C to 150 C IOUT= 2A; VSENSE= 4 V; VCSD= 0 V; Tj= -40C...150C Tj= 25C...150C
K2
IOUT/ISENSE
1590 1760 2140 1600 1760 1930 -8 8 %
dK2/K2
(1)
IOUT= 2A; VSENSE= 4 V; Current sense ratio drift VCSD= 0V; TJ= -40 C to 150 C IOUT= 4A; VSENSE= 4 V; VCSD= 0 V; Tj= -40C...150C Tj= 25C...150C
K3
IOUT/ISENSE
1650 1740 1950 1650 1740 1830 -5 5 %
dK3/K3(1)
IOUT= 4A; VSENSE= 4 V; Current sense ratio drift VCSD= 0V; TJ= -40 C to 150 C IOUT= 0A; VSENSE= 0V; VCSD= 5V; VIN= 0V; Tj= -40C...150C
0
1
A
ISENSE0
Analog sense leakage current
VCSD= 0V; VIN= 5V; Tj= -40C...150C IOUT= 2A; VSENSE= 0V; VCSD= 5V; VIN= 5V; Tj= -40C...150C
0
2
A
0 4
1 20
A mA
IOL
Openload ON state current detection threshold Max analog sense output voltage Analog sense output voltage in overtemperature condition
VIN = 0V, 8VVSENSE
5
V
VSENSEH
VCC= 13V; RSENSE= 10K
9
V
10/31
VNQ5050AK-E Table 8.
Symbol
Electrical specifications Current sense (8VParameter Analog sense output current in overtemperature condition Test conditions Min. Typ. Max. Unit
ISENSEH
VCC= 13V; VSENSE= 5V
8
mA
Delay response time tDSENSE1H from falling edge of CS_DIS pin Delay response time from rising edge of CS_DIS pin
VSENSE<4V, 0.5A50
100
s
tDSENSE1L
5
20
s
Delay response time tDSENSE2H from rising edge of INPUT pin Delay response time between rising edge of tDSENSE2H output current and rising edge of current sense tDSENSE2L Delay response time from falling edge of INPUT pin
80
250
s
65
s
100
250
s
1. Parameter guaranteed by design; it is not tested.
Table 9.
Symbol IlimH IlimL TTSD TR TRS THYST VDEMAG VON
Protection(1)
Parameter DC short circuit current Test conditions VCC=13V 5VShort circuit current VCC=13V; TR7 175 TRS + 5
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device is subjected to abnormal conditions, this software must limit the duration and number of activation cycles.
11/31
Electrical specifications Table 10.
Symbol VIL IIL VIH IIH VI(hyst) VICL VCSDL ICSDL VCSDH ICSDH
VNQ5050AK-E
Logic input
Parameter Input low level voltage Low level input current Input high level voltage High level input current Input hysteresis voltage Input clamp voltage CS_DIS low level voltage Low level CS_DIS current CS_DIS high level voltage High level CS_DIS current VCSD=2.1V 0.25 ICSD= 1mA ICSD= -1mA 5.5 -0.7 7 VCSD=0.9V 1 2.1 10 IIN= 1mA IIN= -1mA VIN= 2.1V 0.25 5.5 -0.7 0.9 7 VIN= 0.9V 1 2.1 10 Test conditions Min. Typ. Max. 0.9 Unit V A V A V V V V A V A V V V
VCSD(hyst) CS_DIS hysteresis voltage VCSCL CS_DIS clamp voltage
Figure 4.
INPUT CS_DIS
Current sense delay characteristics
LOAD CURRENT SENSE CURRENT tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L
12/31
VNQ5050AK-E Figure 5.
Electrical specifications Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled)
VIN
tDSENSE2H
t IOUT
IOUTMAX
90% IOUTMAX
t ISENSE
ISENSEMAX
90% ISENSEMAX
t
Figure 6.
Switching characteristics
VOUT tWon 80% dVOUT/dt(on) tr 10% tf t INPUT td(on) tWoff 90% dVOUT/dt(off)
td(off)
t
13/31
Electrical specifications Figure 7. IOUT/ISENSE Vs. IOUT
VNQ5050AK-E
Iout / Isense
2600
max Tj = -40 C to 150 C
2400 2200 2000 1800
typical value
max Tj = 25 C to 150 C
1600 1400 1200 1000 1
min Tj = 25 C to 150 C
min Tj = -40 C to 150 C
1,5
2
2,5
3
3,5
4
4,5
5
IOUT (A)
Figure 8.
Maximum current sense ratio drift vs load current
dk/k(%)
15 10 5 0 -5 -10 -15 1 1,5 2 2,5
IOUT (A)
3
3,5
4
Note:
Parameter guaranteed by design; it is not tested.
14/31
VNQ5050AK-E Table 11. Truth table
Input L H L H L H L H H L H L Output L H L L L L L L L H H L
Electrical specifications
Conditions Normal operation Overtemperature Undervoltage Short circuit to GND (Rsc 10 m) Short circuit to VCC Negative output voltage clamp
Sense (VCSD=0V)(1) 0 Nominal 0 VSENSEH 0 0 0 0 if Tj < TTSD VSENSEH if Tj > TTSD 0 < Nominal 0
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit.
Figure 9.
Output voltage drop limitation
Vcc-Vout Tj=150oC Tj=25oC Tj=-40oC
Von Iout
Von/Ron(T)
15/31
Electrical specifications Table 12.
ISO 7637-2: 2004(E) Test pulse 1 2a 3a 3b 4 5b(2) ISO 7637-2: 2004(E) test pulse 1 2a 3a 3b 4 5b (2) III C C C C C C III -75 V +37 V -100 V +75 V -6 V +65 V
VNQ5050AK-E
Electrical transient requirements
Test levels IV -100 V +50 V -150 V +100 V -7 V +87 V Number of pulses or test times 5000 pulses 5000 pulses 1h 1h 1 pulse 1 pulse Test level results(1) IV C C C C C C Burst cycle/pulse repetition time Delays and Impedance 2 ms, 10 50 s, 2 0.1 s, 50 0.1 s, 50 100 ms, 0.01 400 ms, 2
0.5 s 0.2 s 90 ms 90 ms
5s 5s 100 ms 100 ms
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b. 2. Valid in case of external load dump clamp: 40V maximum referred to ground.
Class C E
Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
16/31
VNQ5050AK-E
Electrical specifications
2.4
Electrical characteristics curves
Figure 10. Off state output current
Iloff (uA)
0.09 0.08 0.07 0.06 0.05 0.04 2 0.03 0.02 0.01 0 -50 -25 0 25 50 75 100 125 150 175 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Figure 11. High level input current
Iih (uA)
5 4.5
Off state Vcc= 13V Vin= Vout= 0V
4 3.5 3 2.5
Vin= 2.1V
Tc (C )
Tc (C )
Figure 12. Input clamp voltage
Vicl (V)
7 6.8 6.6 6.4 6.2 6 5.8 5.6 5.4 5.2 5 -50 -25 0 25 50 75 100 125 150 175
Figure 13. Input low level
Vil (V)
2 1.8
I 1mA in=
1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
Figure 14. Input high level
Vih (V)
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Figure 15. Input hysteresis voltage
Vhyst (V)
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
17/31
Electrical specifications
VNQ5050AK-E
Figure 16. On state resistance vs. Tcase
Ron (mOhm)
100 90 80 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 150 175
Figure 17. On state resistance vs. VCC
Ron (mOhm)
100 90
I out= 2A Vcc= 13V
80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 40
Tc= 150C Tc= 125C Tc= 25C Tc= -40C
Tc (C )
Vcc (V)
Figure 18. Undervoltage shutdown
Vusd (V)
16 14 12
Figure 19. Turn- On voltage slope
(dVout/dt)on (V/ms)
1000 900 800 700
Vcc= 13V Rl= 6.5Ohm
10 8 6 4
600 500 400 300 200
2 0 -50 -25 0 25 50 75 100 125 150 175
100 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
Figure 20. ILIMH vs. Tcase
Ilimh (A)
25 22.5
Figure 21. Turn- Off voltage slope
(dVout/dt)off (V/ms)
1000 900
Vcc= 13V
20
800 700
Vcc= 13V Rl= 6.5Ohm
17.5 15 12.5 10
600 500 400 300 200
7.5 5 -50 -25 0 25 50 75 100 125 150 175
100 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
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VNQ5050AK-E
Electrical specifications
Figure 22. CS_DIS high level voltage
Vcsdh (V)
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Figure 23. CS_DIS clamp voltage
Vcsdcl (V)
8 7.5
I csd= 1mA
7 6.5 6 5.5 5 4.5 4 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
Tc (C )
Figure 24. CS_DIS low level voltage
Vcsdl (V)
4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C )
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Application information
VNQ5050AK-E
3
Application information
Figure 25. Application schematic
+5V
VCC Rprot CS_DIS Dld C Rprot IINPUT OUTPUT Rprot CURRENT SENSE GND
RSENSE Cext
VGND
RGND
DGND
Note:
Channel 2, 3, 4 have the same internal circuit as channel 1.
3.1
3.1.1
GND protection network against reverse battery
Solution 1: resistor in the ground line (RGND only)
This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1. 2. RGND 600mV / (IS(on)max). RGND (- CC) / (-IGND) V
where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not shared by the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then ST suggests to utilize Solution 2 (see below).
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VNQ5050AK-E
Application information
3.1.2
Solution 2: a diode (DGND) in the ground line.
A resistor (RGND= 1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift ( 600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
3.2
Load dump protection
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds the VCC max DC rating. The same applies if the device is subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table.
3.3
MCU I/Os protection
If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 180k . Recommended values: Rprot = 10k, CEXT= 10nF.
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Application information Figure 26. Waveforms
NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT
VNQ5050AK-E
UNDERVOLTAGE VUSDhyst VCC INPUT CS_DIS LOAD CURRENT SENSE CURRENT VUSD
SHORT TO VCC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT OVERLOAD OPERATION Tj INPUT CS_DIS LOAD CURRENT SENSE CURRENT ILIMH ILIML VSENSEH TR TTSD TRS
current power limitation limitation
thermal cycling SHORTED LOAD NORMAL LOAD
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VNQ5050AK-E
Application information
3.4
Maximum demagnetization energy (VCC = 13.5V)
Figure 27. Maximum turn Off current versus inductance (for each channel)
100
A C B
10
I (A) 1 0,1 1 L (mH) 10 100
A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse VIN, IL
Demagnetization
Demagnetization
Demagnetization
t
Note:
Values are generated with RL = 0. In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B.
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Package and PC board thermal data
VNQ5050AK-E
4
4.1
Package and PC board thermal data
PowerSSO-24 thermal data
Figure 28. PowerSSO-24 PC board
Note:
Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm, PCB thickness=1.6mm, Cu thickness=70m (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 29. Rthj-amb vs. PCB copper area in open box free air condition (one channel ON)
RTHj_amb(C/ W)
55 50 45 40 35 30 0 2 4 6 8 10
PCB Cu heatsink area (cm^ 2)
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VNQ5050AK-E
Package and PC board thermal data
Figure 30. PowerSSO-24 thermal impedance junction ambient single pulse (one channel on)
ZTH (C/ W) 1000
100
Footprint 2 cm2 8 cm2
10
1
0.1 0.0001 0.001 0.01 0.1 1 Time (s) 10 100 1000
Figure 31. Thermal fitting model of a double channel HSD in PowerSSO-24(a)
a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered.
25/31
Package and PC board thermal data Equation 1: pulse calculation formula Z TH = R TH + Z THtp ( 1 - )
where = t p T
VNQ5050AK-E
Table 13.
Thermal parameters
Area/island (cm2) Footprint 0.4 2 6 7.7 9 28 0.001 0.0022 0.025 0.75 1 2.2 4 5 9 17 9 17 8 10 2 8
R1=R7=R9=R11 (C/W) R2=R8=R10=R12 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1=C7=C9=C11 (W.s/C) C2=C8=C10=C12 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C)
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VNQ5050AK-E
Package and packing information
5
5.1
Package and packing information
ECOPACK(R) packages
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of Second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com.
5.2
PowerSSO-24TM mechanical data
Figure 32. PowerSSO-24TM package dimensions
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Package and packing information Table 14. PowerSSO-24TM mechanical data
Millimeters Symbol Min. A A2 a1 b c D E e e3 G G1 H h k L N X Y 4.1 6.5 0.55 5 10.1 2.15 2.15 0 0.33 0.23 10.10 7.4 0.8 8.8 Typ.
VNQ5050AK-E
Max. 2.47 2.40 0.075 0.51 0.32 10.50 7.6
0.1 0.06 10.5 0.4
0.85 10 4.7 7.1
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VNQ5050AK-E
Package and packing information
5.3
Packing information
Figure 33. PowerSSO-24 tube shipment (no suffix)
Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) 49 1225 532 3.5 13.8 0.6
C
B
All dimensions are in mm.
A
Figure 34. PowerSSO-24 tape and reel shipment (suffix "TR")
Reel dimensions
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max)
1000 1000 330 1.5 13 20.2 24.4 100 30.4
Tape dimensions According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm. W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 24 4 12 1.55 1.5 11.5 2.85 2 End
Start Top cover tape No components Components 500mm min No components
500mm min Empty components pockets saled with cover tape. User direction of feed
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Revision history
VNQ5050AK-E
6
Revision history
Table 15.
Date 14-Sep-2004 12-Jan-2006
Document revision history
Revision 1 2 Initial release. Major general update. Reformatted and restructured. Added contents, lists of tables and list of figures. Added Section 3.4: Maximum demagnetization energy (VCC = 13.5V). Added ECOPACK(R) packages information. Added new disclaimer. Figure 14: Input high level and Figure 15: Input hysteresis voltage corrected. Table 4: Absolute maximum ratings : changed EMAX value from 51 to 104 mJ. Table 8: Current sense (8V9-Mar-2007
3
22-Aug-2007
4
01-Oct-2007
5
04-Dec-2007
6
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VNQ5050AK-E
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